1. Technical Field
The present disclosure relates to a MOS (Metal Oxide Semiconductor) semiconductor device of a vertical type, in particular for applications at high operating frequency (for example at radiofrequency, RF), and to a related manufacturing process.
2. Description of the Related Art
FIG. 1 shows a basic, or elementary, structure of a vertical MOS device, in particular an N-channel vertical DMOS (VDMOS—Vertical Double-Diffused Metal Oxide Semiconductor) device, for high-frequency, for example RF, applications, which is designated by 1 and comprises: a substrate of semiconductor material (for example, silicon) that is heavily doped (for example of an N+ type), here not illustrated, and an epitaxial layer 2, which is also of semiconductor material and has the same type of conductivity as the substrate and overlies the substrate. The substrate has the function of drain for the device 1, and the epitaxial layer 2 constitutes a surface extension thereof.
Cells 3 of the device 1 are formed within an active area of the epitaxial layer 2, each comprising a body well 4 having a conductivity opposite to that of the epitaxial layer 2 (in the example, a conductivity of a P type), and a source region 5, within the body well 4, having the same type of conductivity as the substrate 2 (in the example, a conductivity of an N+ type). Each body well 4 is shared by two contiguous cells 3 of the DMOS device 1, and it contains two source regions 5, one for each cell 3, which are arranged between them at a certain lateral distance (in a direction transverse to the vertical direction).
The surface portion of the epitaxial layer 2, arranged at a main top surface 2a thereof, interposed between adjacent body wells 4, is commonly referred to as “intercell region” or “drift region”.
The device 1 further comprises: a gate structure 6, constituted by a first region of dielectric material 7, which is formed above the entire drift region and partially overlies the body wells 4; a gate electrode 8, which is provided on the first region of dielectric material 7, and thus on the drift region, and extends laterally over the body wells 4 and the source regions 5 of two adjacent cells 3; and a second region of dielectric material 9, for example a field-oxide region, overlying the gate electrode 8, except for a central portion thereof, in which a first contact opening 10 is provided.
The first region of dielectric material 7 includes a central portion, which is thick, including field oxide extending over the drift region, and lateral portions, of thin gate oxide, arranged on edge portions of the body wells 4 and on the source regions 5.
The gate electrode 8 has a trapezoidal cross-section, in a way conformable to the underlying region of dielectric material 7, on which the same gate electrode 8 is obtained with deposition techniques.
Through the second region of dielectric material 9 second contact openings 11 are further defined, designed to expose surface portions of the source regions 5 and of the corresponding body well 4 in such a way as to enable electrical connection thereof from outside.
In particular, source metallizations 12, which have an elongated, so-called “finger-shaped”, conformation, are provided on the body wells 4 for contacting the same body wells 4 and the source regions 5. A drain metallization (here not shown) contacts the substrate from the back. In addition, gate metallizations 14, which also have an elongated finger-shaped conformation, comb-fingered to the source metallizations 12, are provided within the first contact openings 10 for contacting the gate electrodes 8.
The channel of each cell 3 is formed in the portion of the corresponding body well 4 arranged directly underneath the gate electrode 8, and is delimited by the junction between the source region 5 and the body well 4 on one side, and by the junction between the body well 4 itself and the drift region of the epitaxial layer 2, on the other side.
The gate electrode 8 is capacitively coupled to the channel for modulating the type of conductivity thereof. In particular, by applying a suitable voltage to the gate electrode 8 it is possible to cause channel inversion and thus create a conductive path for the electrons between the source region 5 (first current-conduction region of the device) and the substrate (second current-conduction region of the device), through the channel and the drift region.
In a way not illustrated, conductive tracks or paths (buses) and contact pads are further provided in a non-active area of the epitaxial layer 2 of the device 1 (i.e., an area not dedicated to formation of the cells 3 and to control of the electric current), for enabling input/output electrical connection from/to the outside world via the source and gate metallizations 12, 14.
Vertical MOS devices that include the above basic structure are, for example, described in U.S. Pat. No. 6,750,512 and U.S. Pat. No. 6,919,252, which were assigned to the present Applicant.
It is known that the technological advancements, for example of radiofrequency systems for applications in the field of telecommunications, satellite communications, radio diffusion, or in the space field (ISM—Interstellar Medium), would benefit from MOS devices that work at high frequencies, for example with values in the 150 to 250 MHz range or higher, at the same time guaranteeing adequate electrical performance, for example in terms of gain and immunity to disturbance.
The present Applicant has found that MOS devices of a known type have certain limitations of a structural type that do not allow adequate performance to be achieved at high operating frequencies. These limitations are linked in particular to the sizing of the channel, with an obvious impact on the parasitic capacitances intrinsically present in the structure.